I am trying to detect when an oscillating signal stops oscillating. I thought the best approach would be to use the ‘stable attribute. When I go to synthesis, it gives an error saying “attribute ‘stable not implemented”.

I am trying to detect when an oscillating signal stops oscillating. I thought the best approach would be to use the ‘stable attribute. When I go to synthesis, it gives an error saying “attribute ‘stable not implemented”.

I am trying to detect when an oscillating signal stops oscillating. I thought the best approach would be to use the ‘stable attribute. When I go to synthesis, it gives an error saying “attribute ‘stable not implemented”.

I am trying to detect when an oscillating signal stops oscillating. I thought the best approach would be to use the ‘stable attribute. When I go to synthesis, it gives an error saying “attribute ‘stable not implemented”.

Say I have a custom record type:

I am using Vivado 2017, trying to work with XADC. This is the block design I am using:block_design_XADC
But I get this duplicated interconnect warning when I try to synthesize the sign after creating the HDL_wrapper:
duplicate warning
When I ignore the warning and try to create the bitstream, it fails again. I don’t know if they are related. But I have no duplicated modules or IPs in my block design. What is actually causing this duplicate warning and how can I resolve it?

so I edited the following vhdl entity

I wrote a code to display ultrasonic HC-SR04 sensor. However, I can’t get data from it, hence seven segment does not display any number. I guess it is related with my constraint. Can you check it?
First topmodule, then constraint code added.