I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in “a_s” and odd ones in “b_s” and this 16 inputs at a time (8 in a and 8 in b).
Each 16 inputs are loaded and used in calculations in the “BFU_SET” for each FSM cycle using indexes calculated from a counter “state_num”.
The issue is that in the simulation the odd values of “state_num” are bypassed and the calculations i want are done only on the even values.