Statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition(vhdl)
There is a code that should switch CHG_UP if the OVR and UND variables are switched.
Statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition(vhdl)
There is a code that should switch CHG_UP if the OVR and UND variables are switched.
What is the utility of a “clock’event” if the sensitivity list has a single signal and is tested at 1?
I was wondering what is the difference between
Is there a way to use a subtype definition to constrain an array element?
Say I have the following type definitions:
How to shutdown VHDL errors “target slice of X elements cannot be assigned a value of Y”?
I have hundreds of VHDL files and Quartus 24.2 decided to raise errors for hundreds of lines.
VHDL if statement precedence
So, this code was given to me to fix, and it made me wonder how it actually should work. The key pitfall here is multiple IF statements in a process that sets/clears the same output. So which one “wins”?
I can not load the initial count to my down counter. The simulation did not work
I designed a down counter with a clk, set_n, load_data, and timer_on. When I put set_n = 0, the down counter is supposed to load_data, set the timer_on = 1, and then keep decreasing the counter until it reaches 0. However, the simulation does not show that my down_counter is working.
Binary cross entropy
I have a question about how write a function cross entropy binary in vhdl the last is
L= -(y*log (ypred)+(1-y)*log(1-ypred) the problem is how can write a log in VHDL , sorry about my English thanks
Difference between using an array and instantiating the internal components in VHDL?
I’m having trouble understanding the difference between or the use of instantiating components instead of directly using an array or std_logic_vector().
cant determine definition of operator =
In line 99, i concatenated keyval1 and keyval2 to get a 16 bit xkey signal.