I have a question while studying Verilog. Let’s say there is a signal called input A; and there is a signal called wire [15:0] B; where assign B[15:0] = {8{A}};

I want to create an interface for AXI-stream with tasks for testbench for sending and receiving data. As far as I understand I have some issues with task visibility in the interface.

Does the SystemVerilog standard permit to mix SystemVerilog files (.sv) with Verilog files (.v)?

Here is my design and testbench environment code.

Here is my design and testbench environment code.

Here is my design and testbench environment code.

`include “fa.v” module FAn(a,b,s,c); parameter size=4; input [size-1:0]a; input [size-1:0]b; output reg [size-1:0]s; output c; wire [size:0] cin; genvar i; for(i=0;i<size;i=i+1)begin FA(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(s[i]),.c(cin[i+1])); end assign c=cin[size]; endmodule Here in instantiation line: FA(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(s[i]),.c(cin[i+1])); in first iteration, I am passing cin[0] signal (cin(cin[0])). Since I haven;t assigned any value to wire[size:0]cin, cin[0] default value should be “z” right, […]

I have been playing with Verilog, and I am just starting. I have implemented several logic gates from NAND which are working, but now I have hit a dead-end when trying to perform on OR on several bits.

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example:

I am trying to get a handle of how simulators treat delay control (via #<delay>) and I am unable to explain the observed difference in the following two snippets: