Why sequence_out is xx in the 2-bit up-counter testbench?
I’m trying to write a 2-bit up counter in Verilog and it must have dff in it’s design. But, when I test it out puts are = xx. Can you please help me to fix it?
why sequence_out is xx in the 2bit up counter test bench?
i’m trying to right a 2 bit up counter in verilog and it must have dff in it’s design but when i test it out puts are = xx . can you please help me to fix it ?
this is the verilog code :