So basically this is a set associative cache simulation. I need to get it working for 2,4,16 and 32 way associative caches. The LRU is a series of deques within a vector, and the cache itself is a vector of longlongs where the least significant bit is the valid bit. I keep getting a few thousand or so less hits than I should be. Testing on 1122102 instructions with target addresses. Just want to know if there’s any errors I’m overlooking here.