Setting a starting position for the constraint random solver
class square; rand bit arr [3][3]; function void pre_randomize(); arr[0][1] = 1; $display (“%p”,arr); endfunction constraint ab_c { foreach (arr[i,j]) { if (arr[i][j] == 1) { if (i > 0 && j > 0 && j < 2 && i < 2) { arr[i+2][j-1] == 1; } else arr[i][j] == 0; } } } I […]
Classes method execution and systemverilog regions
I want to know when does any class method be executed, is it in active region set or re-active region set.
I’m Trying to understand more the time that the design receive the input values from the environment, when the driver toggles the interface signals, is this process happens in the active or re-active region, and also when the monitor samples the DUT signals is this process happens at active or re-active region.
Program Block in Systemverilog
From Systemverilog LRM:
Program variables can only be assigned using blocking assignments. Non-program variables can only be assigned using nonblocking assignments. Using nonblocking assignments with program variables or blocking assignments with design (non-program) variables shall be an error. References to program variables from outside any program block shall be an error.
stream operands require explicit typecast to be used as argument of system task/function
I’ve been using for years $bits with streaming operators:
SystemVerilog – N access controlled devices, all unique by default, need parameter mechanism for allowing them to be grouped
I’d like a parameter like this:
Why does “assign a = a/2” (inside a task) only cause a single value change?
Today I encountered a very peculiar piece of test code, and everyone is stumped at why it operates the way it does. The simplified version of it would look something like this (please pay attention to the fact that the test is written inside a task):
Best way for debugging / logging SystemVerilog Modules
I’m still learning SystemVerilog and encountered an error while trying to debug a module and assign a unique ID.
String triple quotes not getting accepted by simulators
Triple quoted string is supported as per LRM but none of the simulator is able to compile (getting the below error) any lead will help to understand better.
SystemVerilog issue with assignment pattern in port connection
My SystemVerilog is a little bit rusty and I’m trying to reaccquaint myself with it. I have some RTL that looks like this:
How to write constraints in systemverilog
typedef struct packed { logic [3:0] A; logic [3:0] B; } pkt; rand pkt [10] p; How to write constraints to systemverilog so that they are executed simultaneously: A and B had unique combinations A and B had repeatable data a random number of times. For example: A in the range 0-1 B in the […]