Trap handling in RISC V
Is there any way to handle the trap in HW.
mtvec is pointing to the vector base address of the trap. In HW side how it will be point to specific trap?
In Interrupt handling, it jumps handler function using vector_base+mcause*4.
How the trap handled?
How can I pass the official RISC-V tests on a home-made emulator?
I’m developing a risc-v emulator in c++ which covers the RV32I ISA. While i was making all the instructions, I tested them by making some small programs and loading them into the emulator, but i know there are some official test hosted in this repository.