Xilinx PS PCIe Root DMA
I use custom board with ZynqMP as root port, that connected to Jetson AGX Orin EP.
I tested this connection and can transfer data. But i have use DMA for transfering data from PS memory Zynq to Jetson.
I find resource in wiki:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842008/Zynq+UltraScale+PS-PCIe+Linux+Configuration
Does PCIe have signaling for segmentation/reassembly of packets larger than 4KB?
If a packet (say a MWr) larger than 4KB is to be transmitted over PCIe is there any indication in the TLP header or is that fragmentation/reassembly done at the application layer? I think it’s done at the app layer because I can find no meaningful bits in the TLP header that would help indicate the start/end of the larger packet.
I want to utilize the hidden PCIe slot behind the graphics card using a riser cable, but will this cause any issues for my intended use? [closed]
Closed 6 secs ago.