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Parameter Overriding in Verilog

How and where do I perform parameter override to this question? While I try to override it using #, I am receiving a warning stating that the port size does not match to the inputs and outputs or the parameter BIT_N_TB not found. “include “para_over.v” module tb; parameter BIT_N=6; parameter BIT_N_TB; reg [BIT_N-1:0]a,b; reg cin; […]