I am working on RISCV architecture specifically debug module. I am using OpenOCD and GDB to debug my CPU. I have two different CPU connected to the debug module. One of them is 64-bit the other one is 32-bit. Debug module is also 64-bit. My first question is it possible to use those different bit-width CPUs on the same debug module? I read the RISC-V debug spec 0.12. However, I couldn’t find a clear information(maybe I missed).

I am working on RISCV architecture specifically debug module. I am using OpenOCD and GDB to debug my CPU. I have two different CPU connected to the debug module. One of them is 64-bit the other one is 32-bit. Debug module is also 64-bit. My first question is it possible to use those different bit-width CPUs on the same debug module? I read the RISC-V debug spec 0.12. However, I couldn’t find a clear information(maybe I missed).

I am working on RISCV architecture specifically debug module. I am using OpenOCD and GDB to debug my CPU. I have two different CPU connected to the debug module. One of them is 64-bit the other one is 32-bit. Debug module is also 64-bit. My first question is it possible to use those different bit-width CPUs on the same debug module? I read the RISC-V debug spec 0.12. However, I couldn’t find a clear information(maybe I missed).