My initial aim is to understand how debug mode works to design the debug mode of a CPU. I am following the guidelines of the riscv-isa-sim repo to debug a program. The only difference is creating a log while I am debugging. I used the same commands in the tutorial. I analyzed the log and eliminated the loop parts. It is the first several debugging parts explained below(there are many in the continuation of the log file but I didn’t include it. I didn’t include the actual program log too. I started writing it till entering debug rom.)