Cloud computing platforms often default to one CPU. Does this mean I shouldn’t use Parallel Programming?
Almost every cloud instance I can find defaults one CPU. Why is this only one CPU now, and should I expect this to increase in the future?
Do compilers have to be written for each model of CPU?
Do you need to take account of the different processors and their instructions when writing a compiler? Have instructions been standardised? Or what tools and techniques are available to assist with this? E.g. Ignoring machine instructions that are specific to a certain processor model.
Instruction vs data cache usage
Say I’ve got a cache memory where instruction and data have different cache memories (“Harvard architecture”). Which cache, instruction or data, is used most often? I mean “most often” as in time, not amount of data since data memory might be used “more” in terms of amount of data while instruction cache might be used “more often” especially depending on the program.
Can multiple CPU’s / cores access the same RAM simultaneously?
This is what I guess would happen:
Is there genetic relationship between ARM and PDP-11 architectures?
Reading about ARM architecture I found many similarities to PDP-11 architecture which did not exist between ARM and x86.
Performance of single-assignment ADT oriented code on modern CPUs
Working in immutable data with single assignments has the obvious effect of requiring more memory, one would presume, because you’re constantly creating new values (though compilers under the covers do pointer tricks to make this less of an issue).
Can we illustrate a CPU pipeline with a UML sequence diagram?
I study multicore pipelining and the diagrams are not UML sequence diagrams for instance
Can we illustrate a CPU pipeline with a UML sequence diagram?
I study multicore pipelining and the diagrams are not UML sequence diagrams for instance
What are CPU registers?
This question has been bothering me for some time now and today I figured I would Google it. I’ve read some stuff about it and it seemed very similar to what I’ve always known as processor cache.
How long is a typical modern microprocessor pipeline?
I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how much can we expect them to increase and where is the point of reaching diminshing returns in performance gains for longer pipelines?