Counting L2 cache misses and cache accesses with PAPI_L2_TCM and PAPI_L2_TCA gives cache misses greater than cache accesses leading to miss ratio > 1
I am trying to use the PAPI library (v7.1) to count cache misses, cache accesses and get the miss ratio for the L2 cache. My EventSet comprises the total number of cycles (PAPI_TOT_CYC), total cache misses at the L2 level (PAPI_L2_TCM) and total cache accesses at the L2 level (PAPI_L2_TCA).