I’m writing a Makefile for a Verilator project. I want to first build all object files from all my modules and then link all of them with each of the several test benches I have, as I would do with gcc.

Is this possible?

I have thought in doing something like:

compile:
    verilator -Mdir $(PREFIX) --cc --timing --trace --build package1.sv 
    verilator -Mdir $(PREFIX) --cc --timing --trace --build package2.sv
    verilator -Mdir $(PREFIX) --cc --timing --trace --build module1.sv
    verilator -Mdir $(PREFIX) --cc --timing --trace --build module2.sv

testbench1:
    verilator -o testbench1 --main --exe $(PREFIX)/*.o $(PREFIX)/*.a testbench1.sv  

testbench2:
    verilator -o testbench2 --main --exe $(PREFIX)/*.o $(PREFIX)/*.a testbench2.sv  

The problem I have is that the testbench lines keep asking for the package files.