I’m working on implementing a BCD counter in SystemVerilog using T flip-flops (JK with J=K=1). The goal is to count from 0 to 9 and then reset back to 0. I’m using the clr input of a JK flip-flop, intending to reset the flip-flop when the count reaches 4’b1010. However, I’m facing an issue where, upon reaching 4’b1010, the counter resets to 4 instead of 0.

Upon investigation, it seems that the issue might be related to the third flip-flop, as it evaluates both conditions in the always_ff block as true.

my top desgin:

    module bcdCounter(
    input logic clk,
    input logic rst,
    output logic Q0,
    output logic Q1,
    output logic Q2,
    output logic Q3,
    output [3:0] out
    );
    
    
    assign out = {Q3,Q2,Q1,Q0};
    
    logic clr;
    assign clr = ~(Q3 & Q1);
    // $monitor("the value of clr is %0d and Q3 is %d and Q1 is %d", clr,Q3,Q1);
    jkFlipFlop flipFlop1(.J(1'b1), .K(1'b1), .rst(rst), .clk(clk), .clr(clr), .Q(Q0));
    jkFlipFlop flipFlop2(.J(1'b1), .K(1'b1), .rst(rst), .clk(Q0), .clr(clr), .Q(Q1));
    jkFlipFlop flipFlop3(.J(1'b1), .K(1'b1), .rst(rst), .clk(Q1), .clr(clr), .Q(Q2));
    jkFlipFlop flipFlop4(.J(1'b1), .K(1'b1), .rst(rst), .clk(Q2), .clr(clr), .Q(Q3));
    
endmodule

flop code:

module jkFlipFlop(
    input logic J,
    input logic K,
    input logic rst,
    input logic clk,
    input logic clr,
    output logic Q
    );
    
    always_ff @(negedge clk, negedge clr ,posedge rst) begin
        if (rst) begin
            Q <= 1'b0;
        end
        else if(clr == 1'b0) begin
            Q <= 1'b0;
        end
        else if(clr != 1'b0 )begin   
            case ({J,K})
                2'b00: Q <= Q;
                2'b01: Q <= 1'b0;
                2'b10: Q <= 1'b1;
                2'b11: Q <= ~Q; 
             endcase
        end
    end    
endmodule

TB:

module bcdTB();
    logic clk,rst,Q0,Q1,Q2,Q3;
    logic [3:0] out;
    bcdCounter bcdCount(.clk(clk), .rst(rst), .Q0(Q0), .Q1(Q1), .Q2(Q2), .Q3(Q3),.out(out));
    always #40 clk = ~clk;
    
    initial begin
        clk = 1'b0;
        rst = 1'b0;
        #2 rst = 1'b1;
        #2 rst = 1'b0;
       
        #1000
        $finish;
    end
endmodule

simulation:
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