I’m trying to write a simple frequency counter in Verilog and what I found is that if I try to copy my ‘counter’ register I get an error pop-up window saying “There’s a timing error in place and route report. Do you want to continue with the flow?” How to mitigate the issue?
module FreqCounter2(
input wire Clk,
input wire Signal,
output wire [7 : 0] Counter,
output wire [2 : 0]SCKout
);
parameter MEASURE_STATE = 0;
parameter COPY_COUNTER_STATE = 1;
parameter RESET_CLK_COUNTER_STATE = 2;
reg [7 : 0] counter = 0;
reg [7 : 0] counterBuffer_reg = 0;
reg [2 : 0] SignalReg = 0;
reg [2 : 0] state = 0;
assign Counter = counter;
assign SCKout = SignalReg;
assign counterBuffer = counter;
wire SignalRisingEdge = (SignalReg[2:1] == 2'b01); //detect rising edge of the incoming signal
always @(posedge Clk)
begin
case(state)
MEASURE_STATE:
begin
counter <= counter + 1;
if(SignalRisingEdge == 1)
begin
state <= COPY_COUNTER_STATE;
end
end
COPY_COUNTER_STATE:
begin
counterBuffer_reg <= counter; //this line drives me nuts
//When I try to copy counter I get a message:
//"There's a timing error in place and route report. Do you want to continue with the flow?"
state <= RESET_CLK_COUNTER_STATE;
end
RESET_CLK_COUNTER_STATE:
begin
state <= MEASURE_STATE;
counter <= 0;
end
endcase
end
endmodule